Senior Analog IC Layout Engineer

About the role

NXP Semiconductors is looking for an experienced Senior Analog IC Layout Engineer to join the Central Layout Group supporting the Power & Energy Business Line, with a focus on Automotive Power Solutions. The role involves leading layout execution for complex mixed‑signal and power management ICs from planning through tape‑out.

Key responsibilities

• Lead physical implementation of analog and mixed‑signal ICs, defining and optimizing floorplans for complex blocks.
• Drive layout activities from planning to tape‑out, ensuring design quality, robustness and compliance with methodologies.
• Own DRC, LVS, ERC and physical sign‑off, support extraction analysis and post‑layout verification.
• Coordinate with design, verification, package, test and product engineering teams and mentor junior engineers.

Required profile

• Bachelor or Master degree in Electrical Engineering, Electronics, Physics or Microelectronics.
• Strong experience in analog IC layout development using Cadence Virtuoso.
• Ability to work independently on complex technical challenges and communicate effectively in English.

Required skills

• Cadence Virtuoso layout environment.
• DRC/LVS sign‑off methodologies.
• Knowledge of CMOS, BCD, SOI and mixed‑signal design.
• Experience with Calibre, PVS, Quantus, StarRC or equivalent EDA tools.
• Layout automation and scripting (SKILL, Python, TCL, Shell).